
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

ENTITY dmemory IS
	PORT(	read_data			: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
			address				: IN 	STD_LOGIC_VECTOR( 7 DOWNTO 0 );
			write_data			: IN 	STD_LOGIC_VECTOR( 7 DOWNTO 0 );
			MemRead, Memwrite	: IN 	STD_LOGIC;
			clock,reset			: IN 	STD_LOGIC );
END dmemory;

ARCHITECTURE behavior OF dmemory IS
-- Incluido para FPGA com memória sincrona
	component ram
		PORT(
			address	    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			clock		: IN STD_LOGIC  := '1';
			data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			wren		: IN STD_LOGIC ;
			q			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	end component;
-- ***************************************
	SIGNAL lpm_write : STD_LOGIC;
BEGIN

	ram_inst : ram
	PORT MAP (
			data	=> write_data, address	=> address,
			wren	=> lpm_write, clock	=> not clock, q		=> read_data
		);
			
		lpm_write	<= memwrite; --AND (NOT clock);
END behavior;

